1. Field of the Invention
The present invention relates to a timing check circuit which is used with logic analyzing software premised on the usage of logic cells in a specific system, and, more particularly, to a timing check model for checking the input timing specification, interval specification and setup time specification of a functional macro which is constituted of logic cells in a specific system.
2. Description of the Related Art
Conventionally, the timing check of a functional macro constituted of logic cells in a specific system requires logical connection information of that functional macro and a timing check model. The logical connection information is information on circuit connection which is described in a format specified by logic analyzing software, and can generally be edited arbitrarily by a circuit designer. The timing check model describes an operational timing using a specific language that is specified by the logic analyzing software. In general, the timing check model is provided as a library for a flip-flop system constituting a logic cell in a specific system. Therefore, the circuit designer should newly edit the timing check model of the functional macro. But, it is necessary to describe the timings for all the logical combinations of input signals that define the operational timing, so that it is practically almost impossible to prepare the timing check model.
Conventionally, the timing check model of a functional macro was not normally prepared, and visual timing check was executed by monitoring the input timing of the functional macro at the time of executing the logic check and comparing the timing at the change in the input of a measuring terminal with the specified value of the timing of the functional macro.
To avoid the visual timing check, conventionally, there has been proposed the checking scheme that uses a timing model which has a circuit structure as shown in FIG. 1. In FIG. 1, buffer circuits (delay circuits) 33 and 34 are respectively inserted in a data input terminal 31 and a clock input terminal 32 of a flip-flop (FF) 35 constituting a logic cell in a specific system to constitute an FF 7, and timing check is executed for the FF7. The setup time or hold time for the FF 7, which is equivalent to a logic cell, can be inspected by giving delay values to the delay circuits constituted of the buffer circuits 33 and 34.
Assuming that the setup time for the FF 35 of a logic cell in the specific system is 2 ns, the setup time for the input terminal 31 with respect to the clock input terminal 32 of the FF 7 of the logic cell becomes 5 ns by setting the delay value of the delay circuit 34 to 3 ns, so that a timing check can be executed with the setup time of 5 ns for the FF 7 of the logic cell.
As described above, however, the preparation of a timing check model for a functional macro is practically impossible because it takes a vast amount of time to describe the model and also the check of the propriety of the model itself is necessary. Since the check involving the monitoring of the input timings of a functional macro is a visual-based scheme, a great amount of time for the check is required and the chance of overlooking the comparison result increases.
In the timing check scheme shown in FIG. 1, since the specified value of 5 ns of the setup time of the FF 7 of the logic cell is an offset added to the specified value for the FF 35 of the logic cell, the timing check cannot be carried out accurately. More specifically, while the timing that is to be inspected as a setup time should range from 5 ns before the rising of the clock terminal 32 to that rising for the FF 7 of the logic cell, the check cannot be conducted outside the range of 5 ns before the rising of the clock terminal 32 to 3 ns before that rising for the circuit structure shown in FIG. 1. Further, the check of the delay circuit 34 causes the delay time of the FF 7 of the logic cell to vary, disabling the accurate timing check.